One common interface used in computer systems is Peripheral Component Interconnect (PCI) Express (“PCIe”, in accordance with PCI Express Base Specification 3.0, Revision 0.5, August 2008). In today's bridge designs (such as PCI Bridges), power management may be triggered using an “idle timeout counter” mechanism. A timeout counter may generally represent a static guessing mechanism that has no real correlation with the actual traffic activities. For example, the timeout counter mechanism may be solely based on the idle period between two packets.
However, the consequences of a wrong value for idle timeout counter to trigger power management in a bridge may either cause a performance impact with no power saving at all or even hardware compliancy issues. Therefore, to avoid such issues, the timeout counter is usually programmed with a large value for pessimistic and safe guard reasons. But, a large timeout value would in turn directly penalized power saving opportunity.